Embedded face detection application based on local binary patterns

Comunicación presentada al "HPCC", "ICESS" y "CSS" IEEE International Conference on Embedded Software and Systems, ICESS International Symposium on Cyberspace Safety and Security, CSSIn computer vision during the recent years a new paradigm for object detection has stimulated researchers and designers interest. The foundation of this new paradigm is the Local Binary Pattern (LBP) which is a nonparametric operator that efficiently extracts the features of local structures in images. This communication describes a software embedded implementation of LBP based algorithm for object detection, in particular targeting frontal face detection

FPGA implementation of an embedded face detection system based on LEON3

This paper presents an FPGA face detection embedded system. In order achieve acceleration in the face detection process a hardware-software codesign technique is proposed. The paper describes the face detection acceleration mechanism. It also describes the implementation of an IP module that allows hardware acceleration.Comisión Europea MOBY-DIC FP7-IST-248858Ministerio de Ciencia y Tecnología TEC2011-24319Junta de Andalucía P08-TIC-0367

Design Methodology for Face Detection Acceleration

A design methodology to accelerate the face detection for embedded systems is described, starting from high level (algorithm optimization) and ending with low level (software and hardware codesign) by addressing the issues and the design decisions made at each level based on the performance measurements and system limitations. The implemented embedded face detection system consumes very little power compared with the traditional PC software implementations while maintaining the same detection accuracy. The proposed face detection acceleration methodology is suitable for real time applications.Ministerio español de Ciencia y Tecnología TEC2011-24319Junta de Andalucía FEDER P08-TIC-0367

Power-efficient focal-plane image representation for extraction of enriched Viola-Jones features

This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an image representation which dramatically reduces the computational load of the Viola-Jones object detection framework. Additionally, such representation provides richer information than the simple sum of pixels within rectangular regions originally defined in this framework. As a result, more elaborated features could be devised to speed up the execution of the subsequent attentional cascade, boosting thus the performance of the whole algorithm. The proposed circuitry has been successfully implemented in a CMOS prototype smart imager. Experimental results are given, demonstrating the suitability of the approach presented to efficiently deliver enriched Viola-Jones features.Ministerio de Ciencia e Innovación TEC2009-11812Junta de Andalucía P08-TIC-03674Office of Naval Research (USA) N00014111031